The present invention relates to analog-to-digital converters (ADCs). ADCs are utilized routinely in electronic devices to convert analog input voltages into corresponding digital signals for signal processing purposes. There are several types of ADCs such as pipeline ADCs, flash ADCs, and successive approximation register (SAR) ADCs.
SAR ADCs typically include a comparator, a SAR logic circuit, and a digital-to-analog converter (DAC). The converters use a successive approximation algorithm to iteratively convert a given analog input into a corresponding digital code. Each bit of the corresponding digital code is determined using a binary search algorithm. During the first iteration (or first bit trial), the SAR logic circuit sets a most significant bit (MSB) of an N-bit digital code to a value of 1 and transmits the code to the DAC. The DAC generates a corresponding analog voltage (VDAC) based on the value of the code. The comparator then compares the voltage to be converted (VIN) to VDAC. The SAR logic circuit defines the value of the MSB based on the comparator's decision and stores this value in the SAR. This process is iteratively repeated for the remaining bits of the N-bit digital code and the resulting code is a digital approximation of VIN.
A typical SAR ADC trialing cycle can be broken down into four successive phases: (1) DAC settling, (2) amplification, (3) comparator decision, and (4) SAR logic circuit response to comparator decision. ADCs typically implement delay circuits to allow adequate time for logic propagation/DAC settling and amplification to occur. However, these delay circuits vary with process, voltage, and temperature which can decrease the performance of the ADC. The problem is more prevalent when large a number of ADCs are on a single chip. Traditionally, to overcome these problems, the delay circuits were designed to provide fixed delays and to be immune to process, voltage, and temperature effects. However, utilizing fixed delays prevents optimization of the ADCs performance versus the ADC clock, or the ability to dynamically allocate more time to a portion of the conversion cycle that most limits the ADC performance.
The inventors therefore perceive a need in the art for an improved SAR ADC design to account for process, voltage, and temperature effects while maintaining design flexibility.